I've been thinking a lot in he past few days. First I wanted to establish a 32-bit microcode, instead of the current 24 bits. Then I realized that I will need bigger EEPROMs than I already had, and decided to scrap the 32-bits. Now, I think, I'll need to either take away some hardware capability or move to 32 bits.
This afternoon, I was thinking about how wide the microcode needs to be. I decided to do a "final" estimate representing the architecture as it is now. I came up with an estimate of 25 bits, just one over my target. I have 2 microcode bits currently selecting whether to increment or decrement the stack pointer or increment the program counter. If I need, I will probably reclaim one of those bits by making all SP increments or decrements happen in microcode. Although this won't affect most instructions, it will add a cycle to every push, and more importantly add 2 cycles to every JSR, 1 cycle to every RET, and 5 cycles to every INT/RTI pair.
In other news, I have added another temporary register to the design in order to be able to use (zp),Y addressing. This completely fills up the ALU buses, so no more registers can be added. I'm also working on the simulator and a microcode assembler.
Once the microcode issues clear up, I can make a final block diagram. See you then!
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